1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display in which a system board and a timing control board can be used in common in a 60 Hz driving mode and a 120 Hz driving mode without being modified.
2. Discussion of the Related Art
Recently, various flat panel display devices have been developed to reduce weight and volume which are disadvantages of the cathode ray tube. These flat panel display devices may be, for example, a liquid crystal display, a field emission display, a plasma display panel, a light emitting device, and the like.
The liquid crystal display, among the flat panel display devices, is adapted to display an image by adjusting light transmittance of liquid crystal cells depending on a video signal. A liquid crystal display of an active matrix type is advantageous to the display of a moving image in that a switching element is formed for every liquid crystal cell therein. A thin film transistor (TFT) is mainly used as the switching element.
FIG. 1 schematically shows the configuration of a conventional liquid crystal display which is driven at 120 Hz.
Referring to FIG. 1, the conventional liquid crystal display comprises a liquid crystal panel 2 having liquid crystal cells formed respectively in areas defined by n gate lines GL1 to GLn and m data lines DL1 to DLm, a data driver 4 for supplying analog video signals to the data lines DL1 to DLm, a gate driver 6 for supplying scan signals to the gate lines GL1 to GLn, and a timing controller 8 for arranging data red, green and blue (RGB) inputted from an external system board 10 and supplying the arranged data to the data driver 4, and generating a data control signal (DCS) to control the data driver 4 and generating a gate control signal (GCS) to control the gate driver 6.
The liquid crystal panel 2 includes a transistor array substrate and a color filter array substrate bonded to face each other, a spacer for keeping a cell gap between the two array substrates constant, and a liquid crystal filled in a liquid crystal space provided by the spacer (not shown).
The liquid crystal panel 2 further includes thin film transistors (TFTs) formed respectively in the areas defined by the n gate lines GL1 to GLn and the m data lines DL1 to DLm, and liquid crystal cells connected respectively to the TFTs. Each TFT supplies an analog video signal from a corresponding one of the data lines DL1 to DLm to a corresponding one of the liquid crystal cells in response to a scan signal from a corresponding one of the gate lines GL1 to GLn. Each liquid crystal cell can be equivalently expressed as a liquid crystal capacitor Clc because it is provided with a pixel electrode connected to the corresponding TFT, and a common electrode facing the pixel electrode with a liquid crystal interposed therebetween. This liquid crystal cell further includes a storage capacitor Cst connected to the gate line of a previous stage for maintaining an analog video signal charged on the liquid crystal capacitor Clc until a next analog video signal is charged thereon.
The timing controller 8 arranges the data RGB inputted from the external system board 10 for driving the liquid crystal panel 2 and supplies the arranged data to the data driver 4. Also, the timing controller 8 generates the data control signal DCS and the gate control signal GCS using a dot clock DCLK, a data enable signal DE, and horizontal and vertical synchronous signals Hsync and Vsync externally inputted thereto, and applies the generated data control signal DCS and gate control signal GCS to the data driver 4 and gate driver 6, respectively, to control the driving timings thereof.
The gate driver 6 includes a shift register for sequentially generating scan signals, or gate high signals, in response to a gate start pulse GSP and a gate shift clock GSC of the gate control signal GCS from the timing controller 8. This gate driver 6 sequentially supplies the gate high signals to the gate lines GL of the liquid crystal panel 2 to turn on the TFTs connected to the gate lines GL.
The data driver 4 converts the arranged data signals Data from the timing controller 8 into analog video signals in response to the data control signal DCS from the timing controller 8 and supplies analog video signals of one horizontal line to the data lines DL at an interval of one horizontal period in which each scan signal is supplied to each gate line GL. That is, the data driver 4 selects gamma voltages having certain levels based on gray scale values of the data signals Data and supplies the selected gamma voltages to the data lines DL1 to DLm. At this time, the data driver 4 inverts the polarities of the analog video signals to be supplied to the data lines DL1 to DLm in response to a polarity control signal POL.
On the other hand, in order to display a higher-quality image, the liquid crystal display with the above-mentioned configuration must have a higher resolution and a larger size, resulting in an increase in the amount of data to be transmitted. For this reason, a data transmission frequency becomes higher and the number of data transmission lines becomes larger, causing much electromagnetic interference (EMI). In particular, this EMI is mainly generated in digital interfaces between the timing controller of the liquid crystal display and a plurality of data driving integrated circuits (ICs), resulting in the liquid crystal display being unstably driven.
In order to solve the above problem, various data interface methods have recently been adopted for the liquid crystal display to reduce EMI and power consumption in high-speed data transmission. The data interface methods may be, for example, Low-Voltage Differential Signaling (LVDS) using a differential voltage, Mini-LVDS, Reduced Swing Differential Signaling (RSDS), etc.
On the other hand, a comparison will hereinafter be made between interfaces for transmission of data among system boards, timing control boards and liquid crystal panels of liquid crystal displays which are driven at 60 Hz and 120 Hz. The 60 Hz-driven liquid crystal display includes two LVDS ports arranged between the system board and the timing control board, and eight Mini-LVDS ports arranged between the timing control board and the liquid crystal panel. In contrast, the 120 Hz-driven liquid crystal display includes four LVDS ports arranged between the system board and the timing control board, and eight Mini-LVDS ports arranged between the timing control board and the liquid crystal panel.
That is, the amount of data to be processed in the 120 Hz-driven liquid crystal display increases to twice that in the 60 Hz-driven liquid crystal display. As a result, the number of input signal connection pins, a driving method and control signal characteristics are different depending on the respective driving frequencies, which leads to a problem that the type of a timing controller for actual data processing must be different depending on the respective models.